Integrated circuit FIFO memory devices are widely used in consumer and commercial applications. As is well known to those having skill in the art, in a FIFO memory device, data generally is stored in a sequential order as data is written into the device. A FIFO may maintain a write pointer that specifies the location or address to write the next data entry into the FIFO. The write pointer may be incremented for each write operation. A FIFO memory also generally is sequentially read in the same order as it was written. A read pointer may be maintained, and the read pointer also may be incremented for each subsequent read operation. Thus, the data that is first written into a FIFO device generally is also the data that is first read from the FIFO device.
FIFO devices may have many applications, for example as buffer memory. In network applications, FIFOs may be used as a buffer, to store packets of data. Similarly, in telecommunications applications, FIFOs may be used to buffer incoming and/or outgoing signals, such as Time Division Multiple Access (TDMA) radiotelephone communication signals.
FIFO memory devices are described, for example, in U.S. Pat. Nos. 4,750,149 to Miller; 5,999,478 to Proebsting; 6,122,717 to Chan et al.; 6,230,249 to Chan et al.; and 6,243,799 to Chan et al., all of which are assigned to the assignee of the present application, the disclosures of all of which are hereby incorporated herein by reference in their entirety as if set forth fully herein. FIFO memories also are described in U.S. Pat. Nos. 4,847,812 to Lodhi; 6,070,203 to Hawkins et al.; and 6,233,651 to O'Neill et al. Finally, a FIFO memory is described in Product Preview No. SN74ACT53861 entitled 4096×18 Clocked Multiple-Queue (MultiQ™) First-In, First-Out Memory With Three Programmable-Depth Buffers and Cell-Based Flags, published by Texas Instruments Incorporated, June 1994.